In memory systems, including those utilizing dynamic random access memory (DRAM) arrays, column repair circuitry and redundant columns are provided to compensate for defective memory columns. The column repair circuitry disables the defective column and accesses a redundant memory column that effectively replaces the defective memory column. The repair circuitry disables the defective column before attempting to access a target redundant column. However, by disabling the defective column before accessing a redundant column, the column access time of the DRAM is increased.
FIG. 1 illustrates a typical DRAM having a number of columns 102 and a number of redundant columns 104. Each column 102 has a pair of column bit lines 106, 108 coupled to a pair of column select gate transistors 110, 112. The column select gate transistors are coupled to a pair of IO lines, 114 (IO) and 116 (IO-BAR). The IO lines 114,116 are coupled to a sense amplifier 118. The column select gate transistors 110, 112 are disabled or activated by a column select line 124 that is generated by a respective column decoder 120. The column repair circuitry 122 enables or disables a particular column decoder through signal 126. The column repair circuitry 122 receives a column address signal 128 indicating a target column to be accessed. If the column is not defective, an enable signal 126 is transmitted to the appropriate column decoder. If the column is defective, a disable signal 126 is first transmitted to the appropriate column decoder followed by an enable signal 126 to the redundant column decoder.
Typically, a range of columns are accessed at a time. The column repair circuitry 122 disables the column decoders 120 of the defective columns within the access range before the respective redundant columns are accessed. Often it can take several buffer stages to drive the loadings of the disable signals. These buffer stages increase the access time of the redundant columns and thus the overall access time of the DRAM.
Accordingly, there exists a need for a DRAM repair scheme that overcomes these shortcomings.